9:00 am-5:00 pm Rm 209AB: TUTORIAL 1 - ESL Design and Virtual Prototyping of MPSOCs
9:00 am-5:00 pm Rm 210CD: TUTORIAL 2 - Low Power from A to Z
Tutorials 3-6, see Friday

8:00 am-6:00 pm Rm 303CD: IWBDA:International Workshop on Bio-Design Automation at DAC
8:30 am-5:15 pm Rm 206A: DAC Workshop on 'Mobile and Cloud Computing'
11:30 am-2:00 pm Rm 204B: DAC Workshop: More Than Core Competence...What it Takes for Your Career to Survive, and Thrive! Hosted by Women in Electronic Design (WWED)

9:15 am-10:15 am: Gary Smith on EDA: Trends and What's Hot at DAC
10:30 am-11:15 am: The Multiplier Effect: Developing Multi-Core, Multi-OS Applications
11:30 am-12:15 pm: Career Outlook: Job Market 2010
1:30 pm-2:15 pm: Outsourcing Doesn’t Mean Off-shoring— What is it? And, Why do it?
2:30 pm-3:15 pm: EDA Heritage - Meet Verilog Inventor Dr. Moorby and Formal Verification Pioneer Prof. Bryant
3:30 pm-4:15 pm: A Conversation with the 2010 Marie Pistilli Award Winner

10:30 am-11:00 am: Amiq Consulting S.R.L.: The DVT Integrated Development Environment for e and SystemVerilog
11:00 am-11:30 am: IBM Corp.: The Inside Story on IBM's Product Development Transformation
11:30 am-12:00 pm: BEEcube Inc.: Real-Speed Prototyping – BEE3
12:00 pm-12:30 pm: Gary Stringham & Associates, LLC: Conquering Hardware/Firmware Integration Challenges
12:30 pm-1:00 pm: ASIC Analytic, LLC: ASIC Analytic
1:00 pm-1:30 pm: X-FAB Semiconductor Foundries: CMOS and MEMs Integration: New Strategies in Cost/Performance
1:30 pm-2:00 pm: R3 Logic, Inc.: 3-D IC - Package Co-Design with R3Integrator (tm)
2:00 pm-2:30 pm: ExpertIO, Inc.: Verification IP Selection Criteria
2:30 pm-3:00 pm: Ausdia, Inc.: Top 4 1/2 Problems in Timing Closure
3:00 pm-3:30 pm: BEEcube, Inc.: Real-Speed Prototyping – BEE3

10:15 am-12:15 pm: Analog Design Issues
2:00 pm-4:00 pm: Verification Tools/Methodologies

9:00 am-3:00 pm Rm 213D: EDA Roadmap Workshop
11:30 am-1:00 pm Rm Anaheim Marriott, Marquis North Ballroom: Interoperable PDKs are Here to Stay: New Era of Analog/Custom Innovation
6:00 pm-8:00 pm Rm Anaheim Marriott, Marquis North: Synopsys University Reception
6:00 pm-7:30 pm Rm 203A: The Annual Si2 Open Meeting
6:00 pm-8:00 pm Rm Anaheim Marriott, Grand Ballroom E: Synopsys PrimeTime Special Interest Group (SIG) Reception

8:30 am-5:30 pm Rm 207AB: 4th IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y)
9:00 am-5:00 pm Rm 208AB: Choosing Advanced Verification Methods: So Many Possibilities, So Little Time
1:00 pm-4:00 pm Rm 207C: Advances in Process Design Kits Workshop