11:30 am-12:30 pm Rm Ballroom ABC: Echoes of DACs Past: From Prediction to Realization, and Watts Next?, Bernard Meyerson - IBM Corp.

9:15 am-10:15 am: Lucio's Litmus Test: Is Your Start-Up Ready for the 21st Century?
10:30 am-11:15 am: IP Commercialization: Beyond the Code
2:30 pm-3:15 pm: High-School Panel: You Don't Know Jack!
3:30 pm-4:15 pm: Analog Interoperability: What's the ROI?
4:30 pm-5:15 pm: SOC Verification: Are We There Yet?

9:00 am-11:00 am Rm 207AB: 3-D Stacked Die: Now or the Future?
2:00 pm-4:00 pm Rm 207AB: Does IC Design Have a Future in the Clouds?
4:30 pm-6:00 pm Rm 207AB: What’s Cool for the Future of Ultra Low-Power Designs?

9:00 am-11:00 am Rm 209AB: A Decade of NOC Research - Where Do We Stand?
2:00 pm-4:00 pm Rm 209AB: The Analog Model Crisis – How Can We Solve It?
4:30 pm-6:00 pm Rm 209AB: Design Closure for Reliability

9:00 am-11:00 am Rm 207D: Exploiting Concurrency for System-Level Performance
9:00 am-11:00 am Rm 207C: Data Access Times Define Performance!
9:00 am-11:00 am Rm 210AB: Tools for Effective Post-Silicon Validation and Test
9:00 am-11:00 am Rm 210CD: Shapes and Statistics: Manufacturability and Yield
2:00 pm-4:00 pm Rm 207D: Application-Driven Network-On-Chip Design
2:00 pm-4:00 pm Rm 207C: Exploiting FPGA-Specific Features for Robustness and Efficiency
2:00 pm-4:00 pm Rm 210AB: Leakage Estimation and Optimization
2:00 pm-4:00 pm Rm 210CD: Logic Synthesis Is Alive and Kicking
4:30 pm-6:00 pm Rm 207D: Energy-Efficient Embedded Hardware Design and Management
4:30 pm-6:00 pm Rm 207C: Parallel and Efficient Techniques in Circuit Simulation
4:30 pm-6:00 pm Rm 210AB: Thermal Management and Optimization
4:30 pm-6:00 pm Rm 210CD: Catch of the Day in Benchmarking and Optimal Synthesis

12:00 pm-12:30 pm: CISC Semiconductor Des.+Cons. GmbH: SyAD®s Module SIMBA: Connecting Requirements Engineering with System Design and Implementation
12:30 pm-1:00 pm: CoFluent Design: Multicore System Modeling and SystemC-Based Simulation with UML, SysML and MARTE
1:00 pm-1:30 pm: Zocalo Tech, Inc.: Making Life Easier for IP Providers and Users
1:30 pm-2:00 pm: iNoCs: Network-on-Chip Synthesis

9:00 am-11:00 am Rm 208AB: Case Studies in Formal Verification
1:30 pm-3:00 pm Rm 2nd Floor Foyer Adjacent to 208AB: Wednesday User Track Poster Session
3:00 pm-4:00 pm Rm 208AB: Cornered: Dealing with Variability
4:30 pm-6:00 pm Rm 208AB: Front-End Testing and Verification

6:00 pm-7:30 pm Rm 204A: 13th Annual SIGDA Ph.D. Forum / Member Meeting

1:00 pm-3:00 pm: Design Flow Innovations
3:15 pm-4:30 pm: Verification Advances

7:30 am-9:30 am Rm Anaheim Marriott, Marquis Room: Interoperability Breakfast in 3-D: System-Level and Custom Design Standards Coming Right at You
3:00 pm-4:30 pm Rm ACM/ Sigda Univ. Booth: DAC/ISSCC Student Design Contest Presentations